FinFET technology is an emerging semiconductor technology that is being developed to provide effective scaling solutions for field effect transistor (FET) fabrication at, and below, the 22 nanometer (nm) node. FinFET structures include one or more narrow semiconductor fin structures, wherein each semiconductor fin structure is gated on at least two sides thereof. FinFET structures may be formed using silicon-on-insulator (SOI) substrates, as SOI technology provides low source/drain diffusion, low substrate capacitance, and ease of electrical isolation by use of shallow trench isolation structures. FinFETs may be also formed on bulk substrates to reduce wafer cost and/or enable formation of certain devices in the bulk substrate.
The implementation of silicon-germanium channels with high-percentage Ge concentration in FinFET devices is a primary choice for future technology nodes. Indeed, SiGe channels are desirable for state-of-the-art planar and trigate CMOS technologies because, e.g., a p-metal-gate results in a higher than desired threshold voltage. For advanced technology nodes such as 10 nm and beyond, FinFET devices having channel fin heights of 50 nm or greater are being developed to achieve enhanced performance. It is problematic and non-trivial, however, to form SiGe channel fin structures at heights of 50 nm or greater.
For example, while semiconductor fins can be formed by depositing a SiGe layer on a substrate and patterning the SiGe layer to form SiGe fin structures, the ability to deposit a high Ge-percentage (˜50%-75%) SiGe film with a thickness of 30-60 nm is limited and not practically feasible due to the low critical thickness of high-Ge percentage SiGe alloys. Indeed, the formation of a thick SiGe layer results in high density of defects in the SiGe layer, such as stacking faults, due to high lattice mismatch. Moreover, while thin SiGe layers can be grown on the sidewalls of silicon fin structures (with active fin heights greater than 30 nm), such growth results in non-uniform or facetted growth of SiGe layers on the fin sidewalls (110 surfaces). This can result in variation of device performance due to the non-uniform thickness of the SiGe channel layer along the fin width.